In semiconductor fabrication processes, the photo resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch. As feature sizes decrease to 20/22 nm and beyond, various methods are used to address the resolution issue. Particularly, double exposure techniques may be used to maintain resolution using two masks.
Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession. As a result, line spacing in the combined pattern can be reduced while maintaining good resolution. In a method referred to as double dipole lithography (DDL), the patterns to be formed on the layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. The first and second masks are said to have 1-dimensional (1-D) patterns, which can be printed with existing lithographic tools.
Another form of double exposure is referred to as double patterning technology (DPT). Unlike the 1-D approach of DDL, DPT in some cases allows a vertex (angle) to be formed of a vertical segment and a horizontal segment on the same mask. Thus, DPT generally allows for greater reduction in overall IC layout than DDL does. DPT is a layout splitting method analogous to a two coloring problem for layout splitting in graph theory. In its simplest form, the two coloring problem is a way of coloring the vertices (or edge or face) of a graph such that no two adjacent vertices share the same color. Two adjacent vertices connected with an edge should be assigned different colors. Only two “color types” can be assigned. If a 2 color solution exists, the graph is said to be 2-colorable.
An IC layout includes multiple patterns on many layers. The distance between adjacent elements may be too small to be on the same mask, referred to herein as G0-space, but not so small to be beyond the capability of the technology node. Each pattern on a layer is assigned a first or second “color”; the patterns of the first color are formed by a first mask, and the patterns of the second color are formed by a second mask. DPT is computationally intensive because IC layouts have many solutions having different costs, which are evaluated separately. However, many layouts cannot be simply resolved into two masks, i.e. 2-colorable.
FIGS. 1A and 1B show two examples of pattern layouts that present situations that are not 2-colorable. In FIGS. 1A and 1B, the line width is labeled W, the minimum space between lines is labeled S, and the center-to-center pitch between lines is labeled P. The minimum spacing S is a parameter of a particular process technology node; smaller S corresponds to more advanced technology nodes. In FIG. 1A, the segments 50, 52, and 54 form a first pattern 49 with nearby additional patterns 56 and 58. There are three spatial relationships (indicated by dashed lines), which would violate DPT constraints if put in the same mask. Example DPT constraints may include spacing rules, for example, edge of runs must be a further than a certain distance apart, and shape rules, for example, a pattern cannot violate a spacing rule with itself. Spatial relationships that violate DPT constraints when put into the same mask are called G0-space.
In FIG. 1A, patterns 49 and 56 are too close to be put in the same mask, because segment 50 and pattern 56 are too close, violating a spacing rule and forming a G0-space. Thus pattern 49 must be assigned to a different mask from pattern 56. Assigning pattern 49 to mask A, the first mask, and pattern 56 to mask, B, it is noted that patterns 49 and 58 are also too close to be put in the same mask because segment 54 and pattern 58 form another G0-space. Because pattern 49 is already assigned to mask A, then pattern 58 must be assigned to mask B, the second mask. However, patterns 56 and 58 are similarly too close to each other to be put in the same mask, but both are already assigned to the same mask B. Thus, there is no way to distribute the first pattern 49 and the two additional patterns 56 and 58 between two masks A and B without violating a DPT constraint. In terms of graph theory, when the total number of relationships between patterns that violate the minimum spacing for a single mask is odd, an odd cycle is present, and DPT cannot be used without changing the layout.
FIG. 1B shows a similar odd cycle situation. Segments 60, 62 and 64 form a first pattern 59. The patterns 59, 70, 72, 74 and 76 have five relationships (shown by dashed lines) that violate minimum spacing constraints for being formed in the same mask with each other. Because the number of relationships violating the minimum spacing requirements is an odd number, an odd cycle is present, and DPT cannot be used without changing the layout.
Design Rule Checker (DRC) software can systematically check design rules by showing all G0-spaces in a layout design. A designer would enter the necessary design rules, referred to as a deck, into the DRC using its design rule language, such as Standard Verification Rule Format (SVRF) or a software specific Tool Command Language (TCL). The design rules would specify the criteria for a particular spatial relationship to be a G0-space, such as corner-to-corner distance, end-to-end distance, or run-to-end distance. The DRC software would then take the layout input in a standard format, such as Graphic Data System II (GDSII), and produce an output that shows all the spatial relationships that are G0-spaces. Commonly used DRC software includes CALIBRE™ by MENTOR GRAPHICS; HERCULES™ by SYNOPSYS; DIVA™, DRACULA™, ASSURA™, and PVS™ CADENCE DESIGN SYSTEMS.
If a layout cannot be separated into two masks, the problem can be addressed by changing the layout design. The layout design is usually changed manually by a designer reviewing the G0-space output from a DRC software. Changing a layout design is time-consuming, because a designer aims to minimize the total volume of a design and a change often affects structures in other layers. A designer must evaluate many alternate fixes before selecting on the best solution. Additionally, some fixes does not necessarily resolve certain loop combinations. Therefore, improved methods for efficiently resolving DPT constraint violations are desired.